1. Field of the Invention
The present invention relates to a cache system, a cache system control method, and an information processing apparatus.
2. Description of the Related Art
Conventionally, a microprocessor generally carries a cache memory on a chip to solve a bottleneck in memory access. To improve processing performance, the capacity of the cache memory carried on the chip is increasing year after year. While chips with low power consumption are becoming predominant, the proportion of power consumption of the cache memory in power consumption of the microprocessor is increasing. Accordingly, reduction of power consumption in the cache memory has been demanded.
As a method of reducing the power consumption of a cache memory, there is a method in which power consumption at the time of accessing is reduced by dividing a data memory and a tag memory into a plurality of memory areas and accessing only to parts of these memory areas. Recently, because leak power at the time of stopping the access has been regarded as a problem, there is a method in which a set associative system using a plurality of ways is used, a memory area is divided into a plurality of areas, and each of the divided areas is allocated to each way, and power supply to some parts of the memory areas is cut off (for example, see Japanese Patent Application Laid-open No. 2005-316842). By controlling the access to each way, the cache capacity is changed by the memory areas allocated to the ways.
When an access to a certain way is newly prohibited, cache data stored in the way is invalidated. Therefore, write-back of data to a lower-order memory in a lower hierarchy is required. Further, when the cache capacity is decreased, the number of ways is also decreased. Therefore, the frequency of cache misses increases, thereby degrading the performance of the cache. Further, the cache capacity may not be changed to a pattern having a capacity more than the number of ways.
To change the cache capacity, a method of changing the number of indexes can be also employed. An increase of the cache misses is suppressed by maintaining the number of ways. When the cache capacity is to be increased, there is data having an arrangement change by increasing the number of indexes. In the case of changing the number of indexes, write-back of data to the lower-order memory is required not only at the time of decreasing the cache capacity but also at the time of increasing the cache capacity, different from the case of changing the number of ways. Accordingly, there is another problem that the time required for changing the cache capacity increases.